1. Field of the Invention
The present invention relates to a solid state imaging apparatus and a method for driving a solid state imaging apparatus, and more particularly, to a solid state imaging apparatus and a method for driving a solid state imaging apparatus, capable of detecting light over a large dynamic range.
2. Description of the Related Art
FIG. 9 shows a conventional solid state imaging apparatus, and FIG. 10 shows a pixel and its peripheral part of the solid state imaging apparatus shown in FIG. 9. FIG. 11 is a timing chart showing an operation of the circuit shown in FIG. 10.
More specifically, the solid state imaging apparatus 102 shown in FIG. 9 is a CMOS photosensor made up of a pixel array 104 formed on a semiconductor substrate, vertical selection means 106, horizontal selection means 108, a timing generator (TG) 110, an S/H-CDS set 112, and a constant current source set 114A. The pixel array 104 includes a large number of pixels arranged in a matrix fashion. An electric signal is generated by each pixel in response to light incident on the pixel. In accordance with timing pulses generated by the timing generator 110, the pixels are sequentially selected by the vertical selection means 106 and the horizontal selection means 108, and the electric signals generated by the respective pixels are output from the output unit 118 via the horizontal signal line 116.
As shown in FIG. 10, each pixel 120 includes a photodiode 122, a floating diffusion (FD) unit 124 serving as a charge-voltage conversion means for generating a voltage corresponding to the amount of a charge, a transfer gate 126 for connecting the photodiode 122 to the FD element 124 in response to a transfer pulse, a reset gate 128 for connecting the FD element 124 to a power supply Vdd in response to a reset pulse, and an amplification transistor 130 for outputting the voltage of the FD element 124.
The anode of the photodiode 122 is grounded and its cathode is connected to the source of an n-type MOSFET (MOS Field Effect Transistor) serving as the transfer gate 126. The drain of the MOSFET 126 is connected to the FD element 124. A transfer pulse 132 is supplied from the vertical selection means 106 to the gate of the MOSFET 126. The reset gate 128 is also formed with an n-type MOSFET, wherein the source thereof is connected to the FD element 124, the drain is connected to the power supply Vdd, and the gate is connected to the vertical selection means 106 such that a reset pulse 134 is supplied to the gate.
The n-type MOSFET serving as the amplification transistor 130 is connected to the FD element 124, and the drain is connected to the power supply Vdd. An n-type MOSFET serving as an address gate 138 is disposed between the amplification transistor 130 and the vertical signal line 136, wherein an address pulse 140 is supplied to the gate of the n-type MOSFET 138 from the vertical selection means 106. The source of the amplification transistor 130 is connected to the drain of the address gate 138, and the source of the address gate 138 is connected to the vertical signal line 136.
One vertical signal line 136 is disposed for each column of pixels 120 arranged in the matrix fashion, such that the sources of all address gates 138 in the same column are connected to a corresponding vertical signal line 136. One end of each vertical signal line 136 is connected to a constant current source 114 of the constant current source set 114A disposed outside the pixel array 104 so that a constant current is supplied to the vertical signal line 136 from the constant current source 114. The other end of the vertical signal line 136 is connected to the S/H-CDS set 112 disposed outside the pixel array 104.
The S/H-CDS set 112 includes S/H-CDS circuits 146 connected to the respective vertical signal lines 136. First and second sampling pulses 148 and 150 generated by the timing generator 110 is supplied to each S/H-CDS circuit 146. In response to these sampling pulses, the S/H-CDS circuit 146 holds a voltage (light detection voltage) generated by the FD element 124 in accordance with a signal output from the photodiode 122 and output over the vertical signal line 136 by the amplification transistor 130, and also holds a voltage (offset voltage) which is output from the FD element 124 when the FD element 124 is reset. A voltage corresponding to the difference between these two voltages is output from the S/H-CDS circuit 146. When the first and second sampling pulses 148 and 150 are supplied at the same time to the S/H-CDS circuit 146, the offset voltage is held by the S/H-CDS circuit 146. On the other hand, when only the second sampling pulse 150 is supplied to the S/H-CDS circuit 146, the light detection voltage is held.
The output signals from the S/H-CDS circuits 146 connected to the respective vertical signal lines 136 are sequentially selected by the horizontal selection means 108 in accordance with the timing signal generated by the timing generator 110 and supplied via the horizontal signal line 116 to the output unit 118. The output unit 118 outputs the received signals. The output unit 118 is made up of an amplifier, an AGC circuit, and an analog-to-digital converter.
The operation of the solid state imaging apparatus 102 constructed in the above-described manner is described below with reference to FIG. 11, wherein the discussion will focus on the operation of the pixel 120.
In response to the timing pulse supplied from the timing generator 110, the vertical selection means 106 selects one line of the pixel array 104. At time T1, the vertical selection means 106 supplies an address pulse 140 (with a high level) to pixels 120 in the selected line. More specifically, the address pulse 140 is supplied to the address gate 138 of each pixel 120, and the address gate 138 turns on in response to the address pulse 140. As a result, the amplification transistor 130 is connected to the vertical signal line 136.
At time T2 after that, the vertical selection means 106 outputs a reset pulse 134 to turn on the reset gate 128 thereby connecting the FD element 124 to the power supply Vdd. As a result, a charge (electrons) accumulated in the FD element 124 is removed. The voltage of the FD element 124 in the reset state is output over the vertical signal line 136 via the amplification transistor 130. When the address gate 138 is in the on-state, a source follower is formed by the amplification transistor 130 and the constant current source 114, and thus a voltage precisely corresponding to the voltage of the FD element 124 applied to the gate of the amplification transistor 130 is output over the vertical signal line 136 from the amplification transistor 130 with a low output impedance.
Thereafter, at time T3, the timing generator 110 outputs first and second sampling pulses 148 and 150 to the S/H-CDS circuits 146 connected to the respective vertical signal lines 136. In response, each S/H-CDS circuit 146 holds the offset voltage output over the corresponding vertical signal line 136 from the corresponding amplification transistor 130.
At time T4 after that, the vertical selection means 106 outputs a transfer pulse 132 to turn on the transfer gate 126 thereby transferring the charge (electrons) accumulated in the photodiode 122 during the period till T4 to the FD element 124. The FD element 124 generates a voltage corresponding to the transferred charge, and the generated voltage is output over the vertical signal line 136 via the amplification transistor 130 with a low output impedance.
At time T5, the timing generator 110 outputs a second sampling pulse 150 to the S/H-CDS circuits 146 connected to the respective signal lines 136. In response, each S/H-CDS circuit 146 holds the voltage output from the corresponding amplification transistor 130 over the corresponding vertical signal line 136. The S/H-CDS circuit 146 determines the difference between the voltage held at this point of time indicating the light detection voltage and the already-held offset voltage and outputs a resultant differential voltage indicating the amount of light incident on the photodiode 122 including no offset component.
The offset component varies from one pixel 120 to another, and such variation in offset component can cause noise. However, the offset component is removed by the S/H-CDS circuit 146, and thus the output voltage includes no such noise.
The output signals from the S/H-CDS circuits 146 connected to the respective vertical signal lines 136 are sequentially selected by the horizontal selection means 108 in accordance with the timing pulse generated by the timing generator 110 and output over the horizontal signal line 116 and further output as an image signal from the output unit 118.
At time T6, the vertical selection means 106 returns the address pulse 140 to a low level to turn off the address gate 138 thereby disconnecting each amplification transistor 130 from the corresponding vertical signal line 136. At this point of time, the operation of the pixels 120 in one line is completed.
Thereafter, in accordance with the timing pulses generated by the timing generator 110, the vertical selection means 106 sequentially selects the pixels 120 from line by line, and the operation described above is performed for each line. When all lines have been selected by the vertical selection means 106, one frame of image signal generated by all pixels 120 is output.
However, in the conventional solid state imaging apparatus 102 described above, the detectable amount of light is limited to the range in which the charge generated in the photodiode 122 does not overflow, that is, the upper limit of the detectable amount of light is determined by the saturation level of the photodiode 122. If the amount of light exceeds the saturation level, the signal charge transferred to the FD element 124 becomes constant regardless of the amount of light, and thus the voltage generated by the FD element 124 saturates at a constant value. Therefore, in a case in which the aperture and the shutter speed are determined on the basis of a dark part of a scene or a subject, the photodiode 122 will saturate for a bright part of the scene or the subject. Thus, the bright part becomes white in a resultant picture and no image is obtained for such a bright part.
To solve the above problem, Japanese Unexamined Patent Application Publication No. 11-313257 discloses a solid state imaging device in which the dynamic range is expanded by outputting a signal corresponding to the logarithm of the amount of incident light. However, in this solid state imaging device, it takes a long time to charge or discharge a capacitor, which can result in an afterimage. Another problem is that the structure of this solid state imaging device does not allow use of an embedded photodiode (in which, the photodiode is formed below, for example, a p+-layer covered with an insulating film at the top) having an advantage of low noise, and thus a high-quality image cannot be obtained. A still another problem is that a large number of circuit elements are needed and thus it is difficult to achieve a small-sized solid state imaging device.
It is known to expand the dynamic range by changing the shutter speed and thus the charge accumulation time of the photodiode 122, and take pictures such that one picture is taken in a short enough period of time so that no saturation occurs in the photodiode 122 and another picture is taken over a long enough period of time. By mixing the resultant two pictures, a picture with an expanded dynamic range is obtained. However, this technique needs a line memory or a frame memory, which results in increases in device size and cost. Another problem is that because two pictures taken at different times are mixed together, it is difficult to obtain a picture of a moving subject. It is also known to change the charge accumulation time between adjacent lines of pixels. In this technique, no memory is needed. However, in this technique, calculation associated with adjacent lines is needed, and thus the device becomes complicated in structure and large in size. Besides, mixing of two pictures into a single picture results in a reduction in resolution.
In view of the above, the applicant for the present invention has proposed solid state imaging apparatuses and methods of driving solid state imaging apparatuses, which allow expansion of the dynamic range for various imaging conditions, in Japanese Patent Applications Nos. 2001-201601, 2001-276529, and 2001-286457 (hereinafter, referred to as previous patent applications).
In the techniques disclosed in the previous patent applications, an optical signal with a large dynamic range is output in addition to a normal optical signal.
However, in the techniques disclosed in the previous patent applications, a signal with a large dynamic range is generated only when light incident on a photodiode (PD) is so high in intensity that an overflow of a charge occurs, and thus the signal does not vary linearly depending on the amount of light in a low-intensity range. This makes it difficult to precisely calculate the intensity of light from the normal signal and the signal with the large dynamic range. Therefore, those techniques are not suitable for applications such as machine vision or measuring instruments in which determination of the precise amount of light is needed, although the techniques can be used in monitor cameras or the like without encountering significant problems.
When the techniques are applied to color pictures, the inaccuracy in the intensity of light results in inaccuracy in color, that is, the resultant color becomes unnatural. Because of the structure associated with the contact, the FD element has a large dark current. As a result, the signal with the large dynamic signal arising from the charge accumulated in the FD element includes a large dark current. This results in a reduction in the signal-to-noise ratio.